CTLDM7120-M832D surface mount dual, n-channel enhancement-mode silicon mosfets description: the central semiconductor CTLDM7120-M832D is an enhancement-mode dual n-channel field effect transistor, manufactured by the n-channel dmos process, designed for high speed pulsed amplifier and driver applications. this mosfet offers low r ds(on) and low threshold voltage. marking code: cft features: ? esd protection up to 2kv ? low r ds(on) (0.25 max @ v gs =1.5v) ? high current (i d =1.0a) ? logic level compatibility applications: ? switching circuits ? dc - dc converters ? battery powered portable devices maximum ratings: (t a =25c) symbol units drain-source voltage v ds 20 v gate-source voltage v gs 8.0 v continuous drain current (steady state) i d 1.0 a maximum pulsed drain current, tp=10s i dm 4.0 a power dissipation (note 1) p d 1.65 w operating and storage junction temperature t j, t stg -65 to +150 c thermal resistance (note 1) ja 76 c/w electrical characteristics per transistor: (t a =25c unless otherwise noted) symbol test conditions min typ max units i gssf, i gssr v gs =8.0v, v ds =0 10 a i dss v ds =20v, v gs =0 10 a bv dss v gs =0, i d =250a 20 v v gs(th) v ds =10v, i d =1.0ma 0.5 1.2 v v sd v gs =0, i s =1.0a 1.1 v r ds(on) v gs =4.5v, i d =500ma 0.075 0.10 r ds(on) v gs =2.5v, i d =500ma 0.10 0.14 r ds(on) v gs =1.5v, i d =100ma 0.17 0.25 q g(tot) v ds =10v, v gs =4.5v, i d =1.0a 2.4 nc q gs v ds =10v, v gs =4.5v, i d =1.0a 0.25 nc q gd v ds =10v, v gs =4.5v, i d =1.0a 0.65 nc g fs v ds =10v, i d =500ma 4.2 s c rss v ds =10v, v gs =0, f=1.0mhz 45 pf c iss v ds =10v, v gs =0, f=1.0mhz 220 pf c oss v ds =10v, v gs =0, f=1.0mhz 120 pf t on v dd =10v, v gs =5.0v, i d =500ma 25 ns t off v dd =10v, v gs =5.0v, i d =500ma 140 ns notes: (1) fr-4 epoxy pcb with copper mounting pad area of 54mm 2 . tlm832d case r2 (2-august 2011) www.centralsemi.com ? device is halogen free by design
CTLDM7120-M832D surface mount dual, n-channel enhancement-mode silicon mosfets tlm832d case - mechanical outline lead code: 1) gate q1 2) source q1 3) gate q2 4) source q2 5) drain q2 6) drain q2 7) drain q1 8) drain q1 marking code: cft pin configuration www.centralsemi.com r2 (2-august 2011)
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